Welcome to RouteRTL.

A command-line workflow for FPGA development, from project setup through verification and hardware deployment.

$ python3 -m venv .venv && . .venv/bin/activate && pip install routertl

Get started →Documentation

T₁ // capabilities

One command surface runs the whole FPGA loop: locally, in CI, scripted, or driven by an AI agent.

Declarative Project Model

project.yml and ip.yml describe the design. Autodiscovery finds the sources, the dependency resolver orders them, and lock files pin the result. The same description builds on four vendor backends with no vendor TCL.

project.yml → rr synth run → rr bitstream run

Registry, Locks & Provenance

Dependency Management (Cargo for FPGAs): IP resolves from a growing registry with license detection, ip.lock pins every dependency, and provenance and BOM reports record exactly what went into each artifact.

rr pkg search → rr pkg add → ip.lock → rr provenance

Contracts & Requirements

Each requirement stays linked to the tests, assertions, and formal properties that prove it. Coverage maps show which tests actually reached each requirement, and contract gates reject missing or vacuous evidence before it reaches CI.

Explore verification contracts

rr fdd init → rr testgen → rr sim run → rr sim coverage-map

FPGA Rules & Diagnosis

The smart linter enforces design rules for clocking, memory inference, and arithmetic before the tools run. When a vendor tool fails anyway, rr diagnose maps the log to known causes and fixes.

rr linting → rr rules check → rr diagnose

Bench & Bring-up

A SLURM-style queue arbitrates builds and simulations, leases give each user exclusive use of a shared board, and the embedded analyzer (REA) captures live signals from the running silicon.

rr queue submit → rr lease run → rr program verify → rr ila capture

Reviewable Workflows

The full loop runs through one CLI: requirement, lint, simulation, formal, synthesis, bitstream, programming, board evidence, and back to the requirement. Every step leaves an artifact an engineer can review, identical locally, in CI, and under pre-commit gates.

Explore agent workflows

rr loop open → sim → formal → board evidence → rr loop close

These are entry points — browse the full command map Detailed agent workflow and loop table

T₂ // build provenance

Verifiable build provenance.

ip.lock pins what goes into a build; rr provenance proves what came out of it is current for the right part and target. The same records verify installed IP and export as a bill of materials.

Artifact provenance

Is the bitstream current, built from these sources, for this part and target? A non-zero exit gates the flow before a silently-wrong artifact ships.

rr provenance

Integrity checks

Every installed IP file is checked against the SHA-256 recorded in ip.lock — catching tampering, accidental edits, and corrupted downloads.

rr pkg verify

Bill of materials

Every IP with its version, commit, resolved license, tool inventory, and target device — exportable as CycloneDX or SPDX for compliance tooling.

rr bom --export cyclonedx -o sbom.cdx.json

T₃ // requirement to evidence

Review the evidence at every step of the FPGA workflow.

An agent can repeat the flow; an engineer reviews the artifacts. Use rr hardware doctor for the connectivity preflight; board validation is captured by hardware contract runs.

Explore how agents drive the flow

Start the first loop →

what's in the box

Register banks from YAML (VHDL · C · HTML)
Built-in logic analyzer + waveform viewer (RouteWave)
VHDL / Verilog / SystemVerilog in one project
Smart linting across the full hierarchy